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Features
* * * * * * * *
Contactless Read/Write Data Transmission Sensor Input RS > 100 k (Typical) => Data Stream Inverted Radio Frequency fRF from 100 kHz to 150 kHz e5550 Binary Compatible or ATA5570 Extended Mode Small Size, Configurable for ISO/IEC 11784/785 Compatibility 7 x 32-bit EEPROM Data Memory Including 32-bit Password Separate 64-bit Memory for Traceability Data 32-bit Configuration Register in EEPROM to Setup - Data Rate * RF/2 to RF/128, Binary Selectable or * Fixed e5550 Data Rates - Modulation/Coding * FSK, PSK, Manchester, Bi-phase, NRZ - Other Options * Password Mode * Maximum Block Feature * Answer-On-Request (AOR) Mode * Inverse Data Output * Direct Access Mode * Sequence Terminator(s) * Write Protection (Through Lock-bit per Block) * Fast Write Method (5 Kbps versus 2 Kbps) * OTP Functionality * POR Delay up to 67 ms
Multifunctional 330-bit Read/Write RF Sensor Identification IC ATA5570 Preliminary
1. Description
The ATA5570 is a contactless R/W IDentification IC (IDIC(R)) for applications in the 125 kHz frequency range. A single coil, connected to the chip, serves as the IC's power supply and bi-directional communication interface. The antenna and chip together form a transponder or tag. The on-chip 330-bit EEPROM (10 blocks, 33 bits each) can be read and written blockwise from a reader. Block 0 is reserved for setting the operation modes of the ATA5570 tag. Block 7 may contain a password to prevent unauthorized writing. Data is transmitted from the IDIC using load modulation. This is achieved by damping the RF field with a resistive load between the two terminals COIL1 and COIL2. The IC receives and decodes 100% amplitude-modulated (OOK) pulse-interval-encoded bit streams from the base station or reader.
Rev. 4863A-RFID-07/05
2. System Block Diagram
Figure 2-1. RFID System Using ATA5570 Tag
Transponder Power Reader Baseor station Base station
Coil Interface
Controller
Memory
Data
ATA5570
3. Pin Configuration
Figure 3-1. Pinning SO8
NC COIL1 NC SENS 1 2 3 4 8 7 6 5 NC COIL2 NC VSS
Table 3-1.
Pin 1 2 3 4 5 6 7 8
Pin Description
Symbol NC COIL1 NC SENS VSS NC COIL2 NC Function Not connected Antenna pin 1 Not connected Sensor input Ground Not connected Antenna pin 2 Not connected
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4. ATA5570 - Building Blocks
Figure 4-1. Block Diagram
RS VSS SENS POR
Modulator
Analog front end
COIL1
CR
Write decoder
LR
Mode register Memory (264 bit EEPROM) Input register Test logic HV generator
Controller
COIL2
4.1
Analog Front End (AFE)
The AFE includes all circuits which are directly connected to the coil. It generates the IC's power supply and handles the bi-directional data communication with the reader. It consists of the following blocks: * Rectifier to generate a DC supply voltage from the AC coil voltage * Clock extractor * Switchable load between COIL1 and COIL2 for data transmission from tag to the reader * Field gap detector for data transmission from the base station to the tag * ESD protection circuitry
4.2
Data-rate Generator
The data rate is binary programmable to operate at any data rate between RF/2 and RF/128 or equal to any of the fixed e5550/e5551 and T5554 bit rates (RF/8, RF/16, RF/32, RF/40, RF/50, RF/64, RF/100 and RF/128).
4.3
Write Decoder
This function decodes the write gaps and verifies the validity of the data stream according to the Atmel e555x write method (pulse interval encoding).
Bit-rate generator
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4.4
HV Generator
This on-chip charge-pump circuit generates the high voltage required for programming of the EEPROM.
4.5
DC Supply
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regulates this RF source and uses it to generate its supply voltage.
4.6
Power-On Reset (POR)
This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached.
4.7
Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
4.8
Controller
The control-logic module executes the following functions: * Load-mode register with configuration data from EEPROM block 0 after power-on and also during reading * Control memory access (read, write) * Handle write data transmission and write error modes * The first two bits of the reader-to-tag data stream are the opcode, e.g., write, direct access or reset * In password mode, the 32 bits received after the opcode are compared with the password stored in memory block 7
4.9
Mode Register
The mode register stores the configuration data from the EEPROM block 0. It is continually refreshed at the start of every block read and (re-)loaded after any POR event or reset command. On delivery, the mode register is preprogrammed with the value 0014 8000h which corresponds to continuous read of block 0, Manchester coded, RF/64.
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Figure 4-2.
L 1 1
Block 0 Configuration Mapping - e5550 Compatibility Mode
2 0 34 0 1 5 0 6 0 78 0 0 n5 n4 n3 n2 n1 n0 Data Bit Rate RF/(2n + 2) Direct PSK1 9 10 11 12 13 14 15 16 17 18 19 20 1 X-Mode PWD AOR OTP Modulation PSKCF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1 MAXBLOCK 21 22 23 24 25 26 27 28 29 30 31 32
Master Key Lock Bit Note 1), 2)
ST-Sequence Terminator
Fast Write
RF/2 RF/4 RF/8 Res.
0 1
Unlocked Locked
PSK2 PSK3 FSK1 FSK2
Mode-Defeat 1 0 Mode-Defeat 2 0 Manchester Biphase ('50) Biphase ('57) 0 1 1
1) If Master Key = 6 and bit 15 set, then test-mode access is disabled and extended mode is active 2) If Master Key = 9 and bit 15 set, then extended mode is enabled
4.10
Modulator
The modulator consists of data encoders for the following basic types of modulation:
Table 4-1.
Types of e5550-compatible Modulation Modes
Encoding FSK/8, FSK/5 FSK/8, FSK/10 FSK/5, FSK/8 FSK/10, FSK/8 "0" = RF/8; "0" = RF/8; "0" = RF/5; "0" = RF/10; "1" = RF/5 "1" = RF/10 "1" = RF/8 "1" = RF/8
Mode Direct Data Output FSK1a(1) FSK2a FSK1 FSK2
(1) (1) (1)
PSK1(2) PSK2(2) PSK3
(2)
Phase change when input changes Phase change on bit clock if input high Phase change on rising edge of input "0" = falling edge, "1" = rising edge "1" creates an additional mid-bit change "1" = damping on, "0" = damping off 1. A common multiple of bit rate and FSK frequencies is recommended. 2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency.
Manchester Bi-phase NRZ Notes:
Inverse Data
POR Delay
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4.11
Sensor Input
Modulated output data stream depends on the state of the sensor input. The data stream is inverted when external resistance, connected between Sensor input and VSS, is more than RS > 100 k (typical). Otherwise, the output data stream is not inverted ("normal").
4.12
Memory
The memory is a 330-bit EEPROM, which is arranged in 10 blocks of 33 bits each. All 33 bits of a block, including the lock bit, are programmed simultaneously. Block 0 of page 0 contains the mode/configuration data, which is not transmitted during regularread operations. Block 7 of page 0 may be used as a write-protection password. Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lock bit itself) is not re-programmable through the RF field. Blocks 1 and 2 of page 1 contain traceability data and are transmitted with the modulation parameters defined in the configuration register after the opcode "11" is issued by the reader (Figure 5-6 on page 12). These traceability data blocks are programmed and locked by Atmel. Figure 4-3. Memory Map
01 Page 1 1 1 Traceability data Traceability data 32 Block 2 Block 1 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
L L Page 0 L L L L L L
User data or password User data User data User data User data User data User data Configuration data
Not transmitted
32 bits
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4.13 Traceability Data Structure
Block 1 and 2 of page 1 contain the traceability data and are programmed and locked by Atmel during production testing(1). The most significant byte of block 1 is fixed to "E0"hex, the allocation class (ACL) as defined in ISO/IEC 15963-1. The second byte is therefore defined as the manufacturer's ID of Atmel (= "15"hex). The following 8 bits could be used as UID issuer identifier (UID Bit 47 to 40). If not otherwise requested, the 5 most significant bits (customer identification CID) are by default reset (= 00) as the Atmel standard value (other values may be assigned on request to high volume customers as CID) and the least 3 bits (ICR) are used by Atmel for the IC and/or foundry version of the ATA5570. The lower 40 bits of the data, encode the traceability information of Atmel and conform to a unique numbering system. These 40 data bits are divided in two sub-groups, a 5-digit BCD coded lot ID number (LotID - 20 bit) and the binary wafer number (wafer# - 5 bit) concatenated with the sequential die number on wafer (DW - 15 bit).
Note: 1. This is only valid for wafer delivery
Figure 4-4.
ATA5570 Traceability Data Structure
"E0" "15" "00" "41" 8 Bit No. Block 1 Bit value Block 2 Bit No. 1 1 ... ACL 63 MSB 31 LotID ... 12 "557" 8 9 ... MFC ... ... wafer # 12 13 ... 17 18 20 DW ... 31 32 LSB 16 17 CID ... 24 ICR 25 ... LotID 32 0 32
Example:
ACL MFC UID LotID Wafer# DW
Allocation class as defined in ISO/IEC 15963-1 = E0h Manufacturer code of Atmel Corporation as defined in ISO/IEC 7816-6 = 15h UID issuer identifier on request (respectively 5 bit CID and 3 bit ICR) 5-digit lot number, e.g., "41557" 5 bits for wafer# 15 bits encoded as sequential die on wafer number
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5. Operating the ATA5570
5.1 Initialization and POR Delay
The Power-On-Reset (POR) circuit remains active until an adequate voltage threshold has been reached. This in turn triggers the default start-up delay sequence. During this configuration period of about 192 field clocks, the ATA5570 is initialized with the configuration data stored in EEPROM block 0. If the POR delay bit is reset, no additional delay is observed after the configuration period. Tag modulation in regular-read mode will be observed about 3 ms after entering the RF field. If the POR delay bit is set, the ATA5570 remains in a permanent damping state until 8190 internal field clocks have elapsed. TINIT = (192 + 8190 x POR delay) x TC 67 ms; TC = 8 s at 125 kHz
Any field gap occurring during this initialization phase will restart the complete sequence. After this initialization time the ATA5570 enters regular-read mode and modulation starts automatically, using the parameters defined in the configuration register.
5.2
Tag-to-reader Communication
During normal operation, the data stored within the EEPROM is cycled and the COIL1 and COIL2 terminals are load modulated. This resistive load modulation can be detected at the reader module.
5.3
Regular-read Mode
In regular-read mode, data from the memory is transmitted serially, starting with block 1, bit 1, up to the last block (e.g., 7), bit 32. The last block which will be read is defined by the mode parameter field MAXBLK in EEPROM block 0. When the data block addressed by MAXBLK has been read, data transmission restarts with block 1, bit 1. The user may limit the cyclic datastream in regular-read mode by setting the MAXBLK between 0 and 7 (representing each of the 8 data blocks). If set to 7, blocks 1 through 7 can be read. If set to 1, only block 1 is transmitted continuously. If set to 0, the contents of the configuration block (normally not transmitted) can be read. In the case of MAXBLK = 0 or 1, regular-read mode can not be distinguished from block-read mode. Figure 5-1.
MAXBLK = 5
Examples of Different MAXBLK Settings
0 Block 1 Block 4 Block 5 Block 1 Block 2
Loading block 0 MAXBLK = 2 0 Block 1 Block 2 Block 1 Block 2 Block 1
Loading block 0 MAXBLK = 0 Block 0 0 Loading block 0 Block 0 Block 0 Block 0 Block 0
Every time the ATA5570 enters regular- or block-read mode, the first bit transmitted is a logical "0". The data stream starts with block 1, bit 1, continues through MAXBLK, bit 32, and cycles continuously if in regular-read mode. This behavior is different from the original e555x and helps to decode PSK-modulated data.
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5.4 Block-read Mode
With the direct access command, the addressed block is repetitively read only. This mode is called block-read mode. Direct access is entered by transmitting the page access opcode ("10" or "11"), a single "0" bit, and the requested 3-bit block address, when the tag is in normal mode. In password mode (PWD bit set), the direct access to a single block needs the valid 32-bit password to be transmitted after the page access opcode, whereas a "0" bit and the 3-bit block address follow afterwards. In case the transmitted password does not match with the contents of block 7, the ATA5570 tag returns to the regular-read mode.
Note: A direct access to block 0 of page 1 will read the configuration data of block 0, page 0. A direct access to block 3 to 7 of page 1 reads all data bits as zero.
5.5
e5550 Sequence Terminator
The sequence terminator (ST) is a special damping pattern which is inserted before the first block and may be used to synchronize the reader. This e5550-compatible sequence terminator consists of four bit periods with underlaying data values of "1". During the second and the fourth bit period, modulation is switched off (if Manchester coding is activated, then modulation is switched on). Bi-phase modulated data blocks need fixed leading and trailing bits in combination with the sequence terminator to be reliably identified. The sequence terminator may be individually enabled by setting mode bit 29 (ST = "1") in the e5550-compatibility mode (X-mode = "0"). In the regular-read mode, the sequence terminator is inserted at the start of each MAXBLK-limited read data stream. In block-read mode, after any block-write or direct access command, or if MAXBLK was set to "0" or "1", the sequence terminator is inserted before the transmission of the selected block. This behavior is different from former e5550-compatible ICs (T5551, T5554).
Figure 5-2.
Read Data Stream with Sequence Terminator
No terminator Block 1 Block 2 MAXBLK Block 1 Block 2
Regular read mode Sequence terminator Sequence terminator
ST = on
Block 1
Block 2
MAXBLK
Block 1
Block 2
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Figure 5-3.
e5550-compatible Sequence Terminator Waveforms
Bit period Data "1" Data "1" Data "1" Data "1" First Bit Modulation off (on) Modulation off (on)
Sequence
Last bit
Waveforms per different modulation types V Coil PP Manchester bit "1" or "0"
FSK Sequence terminator not suitable for Biphase or PSK modulation
5.6
Reader-to-tag Communication
Data is written to the tag by interrupting the RF field with short field gaps (on-off keying) in accordance with the e5550 write method. The time between two gaps encodes the "0" or "1" information to be transmitted (pulse interval encoding). The duration of the gaps is usually 50 s to 150 s. The time between two gaps is nominally 24 field clocks for a "0" and 54 field clocks for a "1". When there is no gap for more than 64 field clocks after a previous gap, the ATA5570 exits the write mode. The tag starts with the command execution if the correct number of bits were received. If there is a failure detected the ATA5570 does not continue and will enter regular-read mode.
5.7
Start Gap
The initial gap is referred to as the start gap. This triggers the reader-to-tag communication. During this mode of operation, the receive damping is permanently enabled to ease gap detection. The start gap may need to be longer than subsequent gaps in order to be detected reliably. A start gap will be accepted at any time after the mode register has been loaded ( 3 ms). A single gap will not change the previously selected page (by former opcode "10" or "11"). Figure 5-4. Start of Reader-to-tag Communication
Read mode d1 Write mode d0
Sgap
Wgap
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Table 5-1.
Parameters Start gap Write gap Write data in normal mode
Write-data Decoding Scheme
Remark - Normal write mode "0" data "1" data Symbol Sgap Wgap d0 d1 Min 10 8 16 48 Max 50 30 31 63 Unit FC FC FC FC
5.8
Write-data Protocol
The ATA5570 expects to receive a dual-bit opcode as the first two bits of a reader command sequence. There are three valid opcodes: * The opcodes "10" and "11" precede all block-write and direct-access operations for page 0 and page 1 * The RESET opcode "00" initiates a POR cycle * The opcode "01" precedes all test-mode write operations. Any test-mode access is ignored after the master key (bits 1 to 4) in block 0 has been set to "6". Any further modifications of the master key are prohibited by setting the lock bit of block 0 or the OTP bit. Writing has to follow these rules: * Standard write needs the opcode, the lock bit, 32 data bits and the 3-bit address (38 bits total) * Protected write (PWD bit set) requires a valid 32-bit password after opcode and before data and address bits * For the AOR wake-up command an opcode and a valid password are necessary to select and activate a specific tag
Note: The data bits are read in the same order as written.
If the transmitted command sequence is invalid, the ATA5570 enters regular-read mode with the previously selected page (by former opcode "10" or "11"). Figure 5-5. Complete Writing Sequence
Read mode Write mode Read mode
Op-code
Block data
Block address
Programming
Block 0 loading POR
Start gap
Lock bit
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Figure 5-6.
ATA5570 Command Formats
OP 1p* L 1 Data 32 2 Addr 0
Standard write
Protected write
1p*
1
Password
32
L
1
Data
32
2 Addr
0
AOR (wake-up command)
10
1
Password
32
Direct access (PWD = 1)
1p* 1
Password
32
0
2 Addr
0
Direct access (PWD = 0)
1p* 0
2 Addr
0
Page 0/1 regular read
1p* 00 * p = page selector
Reset command
5.9
Password
When password mode is active (PWD = 1), the first 32 bits after the opcode are regarded as the password. They are compared bit-by-bit with the contents of block 7, starting at bit 1. If the comparison fails, the ATA5570 will not program the memory, instead it will restart in regular-read mode once the command transmission is finished.
Note: In password mode, MAXBLK should be set to a value below 7 to prevent the password from being transmitted by the ATA5570.
Each transmission of the direct access command (two opcode bits, 32 bits password, "0" bit plus 3 address bits = 38 bits) needs about 18 ms. Testing all possible combinations (about 4.3 billion) would take about two years.
5.10
Answer-on-request (AOR) Mode
When the AOR bit is set, the ATA5570 does not start modulation in the regular-read mode after loading configuration block 0. The tag waits for a valid AOR data stream ("wake-up command") from the reader before modulation is enabled. The wake-up command consists of the opcode ("10") followed by a valid password. The selected tag will remain active until the RF field is turned off or a new command with a different password is transmitted which may address another tag in the RF field.
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Table 5-2.
PWD 1
ATA5570 - Modes of Operation
AOR 1 Behavior of Tag After Reset Command or POR Answer-on-request (AOR) mode: - Modulation starts after wake-up with a matching password - Programming needs valid password Password mode: - Modulation in regular-read mode starts after reset - Programming and direct access needs valid password Normal mode: - Modulation in regular-read mode starts after reset - Programming and direct access without password De-activate Function Command with non-matching password deactivates the selected tag
1
0
0
--
Figure 5-7.
Answer-on-request (AOR) Mode
Modulation
VCoil 1 - Coil 2
POR
Loading block 0
No modulation because AOR = 1
AOR wake-up command (with valid PWD)
Figure 5-8.
Coil Voltage After Programming of a Memory Block
VCoil 1- Coil 2
5.6 ms Write data to tag Programming and data verification
Read programmed memory block (Block-read mode)
POR/ or
Read block 1..MAXBLK (Regular-read mode)
single gap
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Figure 5-9.
Anticollision Procedure Using AOR Mode
Reader
Init tags with AOR = "1" , PWD = "1"
Tag
Field OFF => ON POWER ON RESET Read configuration
Wait for tW > 2.5 ms
Enter AOR mode
Wait for OPCODE + PWD => "wake up command"
"Select a single tag" Send OPCODE + PWD => "wake up command"
Receive damping ON
NO Password correct ?
YES Send block 1...MAXBLK
Decode data
NO All tags read ?
YES Field ON => OFF
EXIT
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5.11 Programming
When all necessary information has been received by the ATA5570, programming may proceed. There is a clock delay between the end of the writing sequence and the start of programming. Typical programming time is 5.6 ms. This cycle includes a data verification read to grant secure and correct programming. After programming is successfully executed, the ATA5570 enters block-read mode transmitting the block just programmed (Figure 5-8 on page 13).
Note: This timing and behavior is different from the e555x-family predecessors.
6. Error Handling
Several error conditions can be detected to ensure that only valid bits are programmed into the EEPROM. There are two error types, which lead to two different actions.
6.1
Errors During Writing
The following detectable errors could occur during writing data to the ATA5570: * Wrong number of field clocks between two gaps (i.e., not a valid "1" or "0" pulse stream) * Password mode is activated and the password does not match the contents of block 7 * The number of bits received in the command sequence is incorrect Valid bit counts accepted by the ATA5570 are: Password write Standard write AOR wake up Direct access with PWD Direct access Reset command Page 0/1 regular-read 70 bits 38 bits 34 bits 38 bits 6 bits 2 bits 2 bits (PWD = 1) (PWD = 0) (PWD = 1) (PWD = 1) (PWD = 0)
If any of these erroneous conditions are detected, the ATA5570 enters regular-read mode, starting with block 1 of the page defined in the command sequence.
6.2
Errors Before/During Programming
If the command sequence was received successfully, the following error could still prevent programming: * The lock bit of the addressed block is already set In case of a locked block, programming mode will not be entered. The ATA5570 reverts to blockread mode, continuously transmitting the currently addressed block.
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If the command sequence is validated and the addressed block is not write-protected, the new data will be programmed into the EEPROM memory. The new state of the block-write protection bit (lock bit) will be programmed at the same time accordingly. Each programming cycle consists of 4 consecutive steps. 1. Erase block 2. Erase verification (data = "0") 3. Programming 4. Write verification (corresponding data bits = "1") * If a data verification error is detected after an executed data block programming, the tag will stop modulation (modulation defeat) until a new command is transmitted. Figure 6-1. ATA5570 Functional Diagram
Power-on Reset * p = page selector Setup Modes AOR = 0 Regular-read Mode Page 0 addr = 1 to maxblk Page 0 or 1
AOR = 1
AOR Mode
Start Gap gap single gap Modulation Defeat OP(00) command mode Command Decode OP(11..) Page 1 OP(10..) Write OP(1p)*
gap
Block-read Mode addr = current Direct access OP (1p)* OP (1p)*
Page 0 OP(01)
Reset to page 0
Test-mode if master key <> 6 Write
Number of bits Password check Lock bit check Data verification failed Program and Verify
fail fail fail ok
data = old data = old data = old data = new
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7. ATA5570 in Extended Mode (X-mode)
In general, the block 0 setting of the master key (bits 1 to 4) to the value "6" or "9" together with the X-mode bit will enable the extended mode functions. * Master key = "9": Test mode access and extended mode are both enabled. * Master key = "6": Any test mode access will be denied but the extended mode is still enabled. Any other master key setting will prevent the activation of the ATA5570 extended mode options, even when the X-mode bit is set.
7.1
Binary Bit-rate Generator
In extended mode the data rate is binary programmable to operate at any data rate between RF/2 and RF/128 as given in the formula below. Data rate = RF/(2n + 2)
7.2
OTP Functionality
If the OTP bit is set to "1", all memory blocks are write protected and behave as if all lock bits are set to "1". If, additionally, the master key is set to "6", the ATA5570 mode of operation is locked forever (= OTP functionality). If the master key is set to "9", the test-mode access allows the re-configuration of the tag.
Figure 7-1.
L 1 1
Block 0 - Configuration Map in Extended Mode (X-mode)
2 0 34 0 1 5 0 6 0 78 0 0 n5 n4 n3 n2 n1 n0 Data Bit Rate RF/(2n + 2) Direct PSK1 9 10 11 12 13 14 15 16 17 18 19 20 1 X-Mode PWD AOR OTP Modulation PSKCF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1 MAXBLOCK 21 22 23 24 25 26 27 28 29 30 31 32
Master Key Lock Bit Note 1), 2)
ST-Sequence Terminator
Fast Write
RF/2 RF/4 RF/8 Res.
0 1
Unlocked Locked
PSK2 PSK3 FSK1 FSK2
Mode-Defeat 1 0 Mode-Defeat 2 0 Manchester Biphase ('50) Biphase ('57) 0 1 1
1) If Master Key = 6 and bit 15 set, then test-mode access is disabled and extended mode is active 2) If Master Key = 9 and bit 15 set, then extended mode is enabled
Inverse Data
POR Delay
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Table 7-1.
Mode FSK1(1) FSK2(1) PSK1(2) PSK2 PSK3
(2) (2)
ATA5570 Types of Modulation in Extended Mode and Sensor Input RS < 100 k Typical
Direct Data Output Encoding FSK/5, FSK/8; "0" = RF/5; "1" = RF/8 FSK/10, FSK/8; "0" = RF/10; "1" = RF/8 Phase change when input changes Phase change on bit clock if input high Phase change on rising edge of input "0" = falling edge "1" = rising edge on mid-bit Inverse Data Output Encoding FSK/8, FSK/5; "0" = RF/8; "1" = RF/5 (= FSK1a) FSK/8, FSK/10; "0" = RF/8; "1" = RF/10 (= FSK2a) Phase change when input changes Phase change on bit clock if input low Phase change on falling edge of input "1" = falling edge "0" = rising edge on mid-bit
Manchester Bi-phase 1 ('50) Bi-phase 2 ('57) NRZ Notes:
"1" creates an additional mid-bit change "0" creates an additional mid-bit change "0" creates an additional mid-bit change "1" creates an additional mid-bit change "1" = damping on, "0" = damping off "0" = damping on, "1" = damping off
1. A common multiple of bit rate and FSK frequencies is recommended. 2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency.
7.3
Sequence Start Marker
ATA5570 Sequence Start Marker in Extended Mode
Figure 7-2.
Sequence Start Marker 10 Block n 01 Block n 10 Block n 01 Block n 10 Block n 01
Block-read mode
Regular-read mode
10
Block 1
Block 2
MAXBLK
01
Block 1
Block 2
MAXBLK
10
The ATA5570 sequence-start marker is a special damping pattern which may be used to synchronize the reader. The sequence start marker consists of two bits ("01" or "10") which are inserted as header before the first block to be transmitted if the bit 29 in extended mode is set. At the start of a new block sequence, the value of the two bits is inverted.
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7.4 Inverse Data Output
The ATA5570 supports in its extended mode (X-mode) an inverse data output option. If inverse data is enabled, the modulator as shown in Figure 7-3 works on inverted data (see Table 7-1). This function is supported for all basic types of encoding. Table 7-1 shows the modulation, when RS < 100 k typical. Figure 7-3. Data Encoder for Inverse Data Output
Sensor in
PSK1 PSK2 PSK3 Direct/NRZ Mux FSK1 FSK2 Manchester Bi-phase Data output
Intern out data
D Sync
XOR
XOR
Data clock CLK R
Inverse data output
Modulator
7.5
Fast Write
In the optional fast-write mode the time between two gaps is nominally 12 field clocks for a "0" and 27 field clocks for a "1". When there is no gap for more than 32 field clocks after a previous gap, the ATA5570 will exit the write mode. Please refer to Table 7-2 and Figure 5-6 on page 12.
Table 7-2.
Parameters Start gap Write gap
Fast Write Decoding Schemes
Remark - Normal write mode Fast write mode "0" data "1" data "0" data "1" data Symbol Sgap Wngap Wfgap d0 d1 d0 d1 Min 10 8 8 16 48 8 24 Max 50 30 20 31 63 15 31 Unit FC FC FC FC FC FC FC
Write data in normal mode Write data in fast mode
19
4863A-RFID-07/05
20 Figure 7-4.
0 0 1 1 0 8 FC
9 8 9 16 16 1 8 1 8 16 1 8 9 16 12 8 9 16 1 8 9 16
ATA5570 [Preliminary]
Example of Manchester Coding With Data Rate RF/16
1 Data Rate = 16 Field Clocks (FC)
8 FC
Data Stream
Inverted Modulator Signal
Manchester Coded
12
RF Field
4863A-RFID-07/05
4863A-RFID-07/05
Figure 7-5.
1 Data Rate = 16 Field Clocks (FC) 0 0 1 8 FC
1
0
8 FC
Data Stream
Inverted Modulator Signal Bi-phase Coded
8 9 1 8 16 16 1 89 16 1 8 9 16 12 8 9 16 1 89 16
12
Example of Bi-phase Coding With Data Rate RF/16
RF Field
ATA5570 [Preliminary]
21
Figure 7-6.
Example: FSK1a Coding With Data Rate RF/40, Subcarrier f0 = RF/8, f1 = RF/5
0
1
1
0
0
1 Data Rate = 40 Field Clocks (FC)
Inverted Modulator Signal
Data Stream
f0 = RF/8,
f1 = RF/5
15
1
8
1
8
15
15
1
8
22
ATA5570 [Preliminary]
4863A-RFID-07/05
RF Field
4863A-RFID-07/05
Figure 7-7.
1 Data Rate = 16 Field Clocks (FC) 0 0 1 8 FC 8 FC
1
0
Data Stream
Inverted Modulator Signal
Subcarrier RF/2
89 16 1
12
8
16 1 8
16 1
8
16 1
8
16 1
8
Example of PSK1 Coding With Data Rate RF/16
RF Field
ATA5570 [Preliminary]
23
24 Figure 7-8.
0 0 1 1 0 8 FC
89 16 1 8 16 1 8 16 1 8 16 1 8 16 1 8
ATA5570 [Preliminary]
Example of PSK2 Coding With Data Rate RF/16
1 Data Rate = 16 Field Clocks (FC)
8 FC
Data Stream
Inverted Modulator Signal Subcarrier RF/2
12
RF Field
4863A-RFID-07/05
4863A-RFID-07/05
Figure 7-9.
1 Data Rate = 16 Field Clocks (FC) 0 0 1 8 FC
1
0
8 FC
Data Stream
Inverted Modulator Signal Sub-carrier RF/2
89 16 1 8 16 1 8 16 1 8 16 1 8 16 1 8
12
Example of PSK3 Coding With Data Rate RF/16
RF Field
ATA5570 [Preliminary]
25
8. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Maximum DC current into COIL1/COIL2 (t = 1 ms) Maximum AC current into COIL1/COIL2 (f = 125 kHz) Power dissipation (dice)
(1)
Pin 2, 7 2, 7 2, 7
(2)
Symbol Icoil Icoil p Ptot Tamb Tstg
Value 20 20 100 -25 to +105 -40 to +150
Unit mA mA mW C C
Operating ambient temperature range Storage temperature range Notes: 1. Free-air condition, time of application: 1s 2. Data retention reduced at high temperature
9. Operating Characteristics
All parameters given are valid for Tamb = +25C and fcoil = 125 kHz, unless otherwise specified. No. 1 Parameters RF frequency range Supply current (without Tamb = 25C current consumed by the external LC tank Read circuit and without external resistance on Tamb = -25C to +85C sensor input) Coil voltage (AC supply) Necessary for read(1) Clamp voltage Startup time(2) Data retention Programming cycles Sensor Input Resonance capacitor CR Q-factor of coil LR Top = 55C Tstg = 150C Erase all/Write all Trip point resistance (modulation inverted) See Figure 2-1 on page 2 4, 5 10 mA current into COIL1/COIL2 Test Conditions Pin 2, 7 2, 7 Symbol fRF IDD Min 100 Typ 125 1.5 Max 150 3 Unit kHz A T Type*
2.1 2.2
2, 7
IDD
2
4
A
Q
3.1 4 5 6.1 6.2 7 8 9 10
2, 7 2, 7
Vcoil pp Vclamp tstartup tretention tretention ncycle RT CR QL
10 17 2.5 10 96 100,000 50 323 15 100 340 20 20
Vclamp 23 3 50
Vpp Vpp ms year h cycles
Q T Q Q T(3) Q T T Q
200 357 25
k pF
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter, Q = guaranteed based on initial product qualification data, T = directly or indirectly tested during production. Notes: 1. Current into COIL1/COIL2 has to be limited to 20 mA 2. Time from field on to modulation start 3. Tested on wafer basis
26
ATA5570 [Preliminary]
4863A-RFID-07/05
ATA5570 [Preliminary]
10. Reliability
Parameters Electrostatic discharge ESD S.5.1 (Human Body Model) Electrostatic discharge JEDEC A115A (Machine Model) Lifetime in SO8 at Top =150C Symbol Vmax Vmax tL Value 2000 200 1008 Unit V V h
Figure 10-1. Measurement Setup for IDD and Vmod
R BAT68
-
Coil 1
VOUTmax
+
Coil 2
BAT68
11. Ordering Information
Extended Type Number ATA5570-TAQY (ATA557001-DDW) planned Package SO8 Wafer Remarks - -
12. Package Information
Package SO8
Dimensions in mm
5.00 4.85 1.4 0.4 1.27 3.81 8 5 0.25 0.10 0.2 3.8 6.15 5.85 5.2 4.8 3.7
technical drawings according to DIN specifications
1
4
27
4863A-RFID-07/05
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